Home automation system refers to the automated or remotely controlled household features that are generally aimed to improve the quality of life. In the technology era, various smartphone-based home automation system is developed. However, this kind of design might not be suitable for the elderly and disabled population due to their technological literacy in handling smart devices. The motivation of this project is to assist their daily activities when they are alone or not under care to help them live more independently. This paper presents the designing of a home automation system for elderly and disabled using verilog algorithm. The developed home automation system included front-end digital Integrated Circuit (IC) design up to logic synthesis process using Synopsys and was implemented on an Altera Field Programmable Gate Array (FPGA) using Quartus II. This system incorporated alert features besides common household controlling features and it was successfully prototyped using FPGA. The RTL was synthesized into a gate-level netlist and the lowest clock period 8 ns while slack for setup time and hold time are 1.64 ns and 0.18 ns